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HM5164400 Series HM5165400 Series
64 M FP DRAM (16-Mword x 4-bit) 8 k Refresh/4 k Refresh
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ADE-203-812B (Z) Rev. 1.0 Feb. 27, 1998 Description
The Hitachi HM5164400 Series, HM5165400 Series are 64M-bit dynamic RAMs organized as 16,777,216word x 4-bit. They have realized high performance and low power by employing CMOS process technology. The HM5164400 Series, HM5165400 Series offer Fast Page Mode as a high speed access mode. They have the package variations of standard 32-pin plastic SOJ and standard 32-pin plastic TSOPII.
Features
* Single 3.3 V supply: 3.3 V 0.3 V * Access time: 50 ns/60 ns (max) * Power dissipation Active: 396 mW/360 mW (max) (HM5164400 Series) : 468 mW/396 mW (max) (HM5165400 Series) Standby : 1.8 mW (max) (CMOS interface) : 0.54 mW (max) (L-version) * Fast page mode capability * Refresh cycles #$-only refresh 8192 cycles /64 ms (HM5164400) /128 ms (HM5164400L) (L-version) 4096 cycles /64 ms (HM5165400) /128 ms (HM5165400L) (L-version) CBR/Hidden refresh 4096 cycles /64 ms (HM5164400, HM5165400) /128 ms (HM5164400L, HM5165400L) (L-version)
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HM5164400 Series, HM5165400 Series
* 4 variations of refresh #$-only refresh $-before-#$ refresh Hidden refresh Self refresh (L-version) * Battery backup operation (L-version) Ordering Information
Type No. HM5164400J-5 HM5164400J-6 HM5164400LJ-5 HM5164400LJ-6 HM5165400J-5 HM5165400J-6 HM5165400LJ-5 HM5165400LJ-6 HM5164400TT-5 HM5164400TT-6 HM5164400LTT-5 HM5164400LTT-6 HM5165400TT-5 HM5165400TT-6 HM5165400LTT-5 HM5165400LTT-6 Access time 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 400-mil 32-pin plastic TSOP II (TTP-32DC) Package 400-mil 32-pin plastic SOJ (CP-32DC)
2
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HM5164400 Series, HM5165400 Series
Pin Arrangement (HM5164400 Series)
32-pin SOJ 32-pin TSOP
VCC I/O0 I/O1 NC NC NC NC WE RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V SS I/O3 I/O2 NC NC NC CAS OE A12 A11 A10 A9 A8 A7 A6 V SS
VCC I/O0 I/O1 NC NC NC NC WE RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V SS I/O3 I/O2 NC NC NC CAS OE A12 A11 A10 A9 A8 A7 A6 V SS
(Top view)
(Top view)
Pin Description
Pin name A0 to A12 Function Address input * * I/O0 to I/O3 Row/Refresh address A0 to A12 Column address A0 to A10
Data input/output Row address strobe Column address strobe Write enable Output enable Power supply Ground No connection
5$6 &$6 :( 2(
VCC VSS NC
3
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HM5164400 Series, HM5165400 Series
Pin Arrangement (HM5165400 Series)
32-pin SOJ 32-pin TSOP
VCC I/O0 I/O1 NC NC NC NC WE RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V SS I/O3 I/O2 NC NC NC CAS OE NC A11 A10 A9 A8 A7 A6 V SS
VCC I/O0 I/O1 NC NC NC NC WE RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V SS I/O3 I/O2 NC NC NC CAS OE NC A11 A10 A9 A8 A7 A6 V SS
(Top view)
(Top view)
Pin Description
Pin name A0 to A11 Function Address input * * I/O0 to I/O3 Row/Refresh address A0 to A11 Column address A0 to A11
Data input/output Row address strobe Column address strobe Write enable Output enable Power supply Ground No connection
5$6 &$6 :( 2(
VCC VSS NC
4
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HM5164400 Series, HM5165400 Series
Block Diagram (HM5164400 Series)
RAS CAS WE OE
Timing and control
A0 A1 to A10 * * * Column address buffers
Column decoder
16M array
16M array Row decoder * * * I/O buffers 16M array I/O0 to I/O3
Row address buffers
16M array
A11 A12
5
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HM5164400 Series, HM5165400 Series
Block Diagram (HM5165400 Series)
RAS CAS WE OE
Timing and control
A0 A1 to A11 * * * Column address buffers
Column decoder
16M array
16M array
Row decoder
* * *
I/O buffers 16M array
I/O0 to I/O3
Row address buffers
16M array
6
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HM5164400 Series, HM5165400 Series
Operation Table
5$6
H L L L L L H to L L
&$6
x L L L L H L L
:(
x H L* L* x H H
2 2
2(
x L x H L to H x x H
I/O 0 to I/O 3 High-Z Dout Din Din Dout/Din High-Z High-Z High-Z
Operation Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle
H to L
5$6-only refresh cycle &$6-before-5$6 refresh cycle or
Self refresh cycle (L-version) Read cycle (Output disabled)
Notes: 1. H: VIH (inactive), L: VIL (active), x: VIH or VIL 2. tWCS 0 ns: Early write cycle tWCS < 0 ns: Delayed write cycle
Absolute Maximum Ratings
Parameter Terminal voltage on any pin relative to VSS Power supply voltage relative to VSS Short circuit output current Power dissipation Storage temperature Symbol VT VCC Iout PT Tstg Value -0.5 to VCC + 0.5 ( 4.6 V (max)) -0.5 to +4.6 50 1.0 -55 to +125 Unit V V mA W C
DC Operating Conditions
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range VIH VIL Ta Min 3.0 0 2.0 -0.3 0 Typ 3.3 0 -- -- -- Max 3.6 0 VCC + 0.3 0.8 70 Unit V V V V _C Notes 1, 2 2 1 1
Notes: 1. All voltage referred to VSS. 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
7
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HM5164400 Series, HM5165400 Series
DC Characteristics (HM5164400 Series)
HM5164400 -5 Parameter Operating current* * Standby current
1, 2
-6 Max 110 2 Min -- -- Max 100 2 Unit mA mA Test conditions tRC = min TTL interface 5$6, &$6 = VIH Dout = High-Z CMOS interface 5$6, &$6 VCC - 0.2 V Dout = High-Z
Symbol Min ICC1 ICC2 -- --
--
0.5
--
0.5
mA
Standby current (L-version)
ICC2
--
150
--
150
A
5$6, &$6 V
Dout = High-Z tRC = min
CMOS interface
CC
- 0.2 V
5$6-only refresh current*
Standby current*
1
2
ICC3 ICC5 ICC6
-- -- -- -- --
110 5 110 90 500
-- -- -- -- --
100 5 100 80 500
mA mA mA mA A
5$6 = V , &$6 = V
IH
IL
Dout = enable
&$6-before-5$6 refresh
current Fast page mode current* *
4 1, 3
tRC = min
ICC7 ICC10
5$6 = VIL , &$6 cycle, tPC = tPC min
CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 s tRAS 0.3 s
Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
ICC11
--
400
--
400
A
5$6, &$6 0.2 V
Dout = High-Z 0 V Vin VCC + 0.3 V 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
CMOS interface
ILI ILO VOH VOL
-5 -5 2.4 0
5 5 VCC 0.4
-5 -5 2.4 0
5 5 VCC 0.4
A A V V
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while 5$6 = VIL. 3. Measured with one sequential address change per fast page mode cycle, tPC. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
8
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HM5164400 Series, HM5165400 Series
DC Characteristics (HM5165400 Series)
HM5165400 -5 Parameter Operating current* * Standby current
1, 2
-6 Max 130 2 Min -- -- Max 110 2 Unit mA mA Test conditions tRC = min TTL interface 5$6, &$6 = VIH Dout = High-Z CMOS interface 5$6, &$6 VCC - 0.2 V Dout = High-Z
Symbol Min ICC1 ICC2 -- --
--
0.5
--
0.5
mA
Standby current (L-version)
ICC2
--
150
--
150
A
5$6, &$6 V
Dout = High-Z tRC = min
CMOS interface
CC
- 0.2 V
5$6-only refresh current*
Standby current*
1
2
ICC3 ICC5 ICC6
-- -- -- -- --
130 5 130 90 500
-- -- -- -- --
110 5 110 80 500
mA mA mA mA A
5$6 = V , &$6 = V
IH
IL
Dout = enable
&$6-before-5$6 refresh
current Fast page mode current* *
4 1, 3
tRC = min
ICC7 ICC10
5$6 = VIL , &$6 cycle, tPC = tPC min
CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 s tRAS 0.3 s
Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
ICC11
--
400
--
400
A
5$6, &$6 0.2 V
Dout = High-Z 0 V Vin VCC + 0.3 V 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
CMOS interface
ILI ILO VOH VOL
-5 -5 2.4 0
5 5 VCC 0.4
-5 -5 2.4 0
5 5 VCC 0.4
A A V V
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while 5$6 = VIL. 3. Measured with one sequential address change per fast page mode cycle, tPC. 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
9
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HM5164400 Series, HM5165400 Series
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. 5$6, &$6 = VIH to disable Dout.
10
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HM5164400 Series, HM5165400 Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) *1, *2, *19
Test Conditions * * * * Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5164400/HM5165400 -5 Parameter Random read or write cycle time Symbol tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tOED tDZO tDZC tT Min 90 30 8 50 13 0 8 0 8 18 13 13 50 5 13 0 0 3 Max -- -- -- 10000 10000 -- -- -- -- 37 25 -- -- -- -- -- -- 50 -6 Min 110 40 10 60 15 0 10 0 10 20 15 15 60 5 15 0 0 3 Max -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4 Notes
5$6 precharge time &$6 precharge time 5$6 pulse width &$6 pulse width
Row address setup time Row address hold time Column address setup time Column address hold time
5$6 to &$6 delay time 5$6 to column address delay time 5$6 hold time &$6 hold time &$6 to 5$6 precharge time 2( to Din delay time 2( delay time from Din &$6 delay time from Din
Transition time (rise and fall)
11
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HM5164400 Series, HM5165400 Series
Read Cycle
HM5164400/HM5165400 -5 Parameter Access time from 5$6 Access time from &$6 Access time from address Access time from 2( Read command setup time Read command hold time to &$6 Read command hold time to 5$6 Column address to 5$6 lead time Column address to &$6 lead time Symbol tRAC tCAC tAA tOEA tRCS tRCH tRRH tRAL tCAL tCLZ tOH tOHO tOFF tOEZ tCDD Min -- -- -- -- 0 0 0 25 25 0 3 3 -- -- 13 Max 50 13 25 13 -- -- -- -- -- -- -- -- 13 13 -- -6 Min -- -- -- -- 0 0 0 30 30 0 3 3 -- -- 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- 15 15 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9
&$6 to output in low-Z
Output data hold time Output data hold time from 2( Output buffer turn-off time Output buffer turn-off to 2(
&$6 to Din delay time
Write Cycle
HM5164400/HM5165400 -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to 5$6 lead time Write command to &$6 lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tWP tRWL tCWL tDS tDH Min 0 8 8 13 13 0 8 Max -- -- -- -- -- -- -- -6 Min 0 10 10 15 15 0 10 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
12
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HM5164400 Series, HM5165400 Series
Read-Modify-Write Cycle
HM5164400/HM5165400 -5 Parameter Read-modify-write cycle time Symbol tRWC tRWD tCWD tAWD tOEH Min 131 73 36 48 13 Max -- -- -- -- -- -6 Min 155 85 40 55 15 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
5$6 to :( delay time &$6 to :( delay time Column address to :( delay time 2( hold time from :(
Refresh Cycle
HM5164400/HM5165400 -5 Parameter Symbol tCSR tCHR tWRP tWRH tRPC Min 5 8 0 8 5 Max -- -- -- -- -- -6 Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes
&$6 setup time (CBR refresh cycle) &$6 hold time (CBR refresh cycle) :( setup time (CBR refresh cycle) :( hold time (CBR refresh cycle) 5$6 precharge to &$6 hold time
Fast Page Mode Cycle
HM5164400/HM5165400 -5 Parameter Fast page mode cycle time Fast page mode 5$6 pulse width Access time from &$6 precharge Symbol tPC tRASP tCPA tCPRH Min 35 -- -- 30 Max -- -6 Min 40 Max -- Unit ns 16 9, 17 Notes
100000 -- 30 -- -- 35
100000 ns 35 -- ns ns
5$6 hold time from &$6 precharge
13
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HM5164400 Series, HM5165400 Series
Fast Page Mode Read-Modify-Write Cycle
HM5164400/HM5165400 -5 Parameter Symbol Min 76 53 Max -- -- -6 Min 85 60 Max -- -- Unit ns ns 14 Notes
Fast page mode read-modify-write cycle tPRWC time
:( delay time from &$6 precharge
Refresh (HM5164400 Series)
Parameter Refresh period Refresh period (L-version)
tCPW
Symbol tREF tREF
Max 64 128
Unit ms ms
Note 8192 cycles 8192 cycles
Refresh (HM5165400 Series)
Parameter Refresh period Refresh period (L-version) Symbol tREF tREF Max 64 128 Unit ms ms Note 4096 cycles 4096 cycles
Self Refresh Mode (L-version)
HM5164400L/HM5165400L -5 Parameter Symbol tRASS tRPS tCHS Min 100 90 -50 Max -- -- -- -6 Min 100 110 -50 Max -- -- -- Unit s ns ns Notes 23 23
5$6 pulse width (Self refresh) 5$6 precharge time (Self refresh) &$6 hold time (Self refresh)
Notes: 1. AC measurements assume tT = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing 5$6-only refresh or &$6-before-5$6 refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA.
14
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HM5164400 Series, HM5165400 Series
5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that tRCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that tRAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. tDS, tDH are referred to &$6 leading edge in early write cycles and to :( leading edge in delayed write or read-modify-write cycles. 16. tRASP defines 5$6 pulse width in fast page mode cycles. 17. Access time is determined by the longest among tAA, tCAC and tCPA. 18. In delayed write or read-modify-write cycles, 2( must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 20. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms period on the condition a and b below. a. Enter self refresh mode within 15.6 s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6s after exiting from self refresh mode. 21. In case of entering from 5$6-only-refresh, it is necessary to execute CBR refresh before and after self refresh mode according as note 20. 22. For L-version, it is available to apply each 128 ms and 31.2 s instead of 64 ms and 15.6 s at note 20. 23 At tRASS > 100 s, self refresh mode is activated, and not activated at t RASS < 10 s. It is undefined within the range of 10 s tRASS 100 s. For tRASS 10 s, it is necessary to satisfy tRPS. 24. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
15
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HM5164400 Series, HM5165400 Series
Timing Waveforms*24
Read Cycle
tRC tRAS RAS tCSH tRCD tT CAS tRAD tASR tRAH tASC tRAL tCAL tCAH tRSH tCAS tCRP
tRP
Address
Row
Column tRRH tRCH
tRCS
WE
tDZC
tCDD High-Z
Din
tDZO
tOEA
tOED
OE tCAC tAA tRAC tCLZ Dout tOFF tOH Dout tOEZ tOHO
16
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HM5164400 Series, HM5165400 Series
Early Write Cycle
tRC tRAS tRP
RAS tCSH tRCD tT CAS tRSH tCAS tCRP
tASR
tRAH
tASC
tCAH
Address
Row
Column
tWCS
tWCH
WE
tDS
tDH
Din
Din
Dout
High-Z*
* t WCS
t WCS (min)
17
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HM5164400 Series, HM5165400 Series
Delayed Write Cycle*
18
tRC tRAS
tRP
RAS tCSH tRCD tT CAS tASR tRAH tASC tCAH tRSH tCAS tCRP
Address
Row
Column tCWL tRCS tRWL tWP
WE
tDZC
tDS
tDH
Din
High-Z
Din tOED
tDZO
tOEH
OE tOEZ tCLZ High-Z Invalid Dout
Dout
18
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HM5164400 Series, HM5165400 Series
Read-Modify-Write Cycle*
18
tRWC tRAS RAS tT tRCD tCAS
tRP
tCRP
CAS tRAD tASR tRAH tASC tCAH
Address
Row tRCS
Column tCWD tAWD tRWD tCWL tRWL tWP
WE tDZC tDH
tDS High-Z
Din
Din tOED tOEH
tDZO tOEA OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ
19
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HM5164400 Series, HM5165400 Series
#$ #$-Only Refresh Cycle
t RC t RAS RAS t RP

tT t CRP t RPC t CRP CAS t ASR t RAH Address Row t OFF Dout High-Z
20
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HM5164400 Series, HM5165400 Series
$ $-Before-#$ Refresh Cycle #$
t RC t RP t RAS t RP t RAS t RC t RP
RAS tT t RPC t CP t CSR t CHR t RPC t CP t CRP t CSR t CHR
CAS t WRP t WRH WE t WRP t WRH
Address
t OFF Dout High-Z

21
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HM5164400 Series, HM5165400 Series
Hidden Refresh Cycle
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
RAS tT t RSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t RAL t CAH t CHR t CRP
Column
t RCS WE
t RRH t RCH
t DZC High-Z Din
t CDD
t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout
t OED
t OEZ t OHO t OFF t OH
22
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HM5164400 Series, HM5165400 Series
Fast Page Mode Read Cycle
t RASP t CPRH t RP
RAS tT t CSH t RCD CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP
t RCS tRCS WE t DZC t CDD Din t DZO High-Z t OED t DZC t CDD High-Z t DZO t OED tRCH tRCH
t RCS
t RRH t RCH
t DZC t CDD High-Z t DZO t OED
OE t RAC t AA t OEA t CAC t CLZ Dout Dout 1 t OH t CPA t AA t OHO t OEA t CPA t AA t OHO t OFF t OEZ Dout 2 t OEA t CAC t CLZ Dout N t OFF t OEZ
t OH
t OH t OHO
t OFF t CAC t OEZ t CLZ
23
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HM5164400 Series, HM5165400 Series
Fast Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP
CAS
t ASR t RAH
t ASC t CAH
t ASC t CAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z*
* t WCS
t WCS (min)
24
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HM5164400 Series, HM5165400 Series
Fast Page Mode Delayed Write Cycle*
18
t RASP t RP
RAS
tT t CSH t RCD
CAS
t CP t PC t CAS t CAS
t CP t RSH t CAS
t CRP
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout
High-Z
Invalid Dout Invalid Dout Invalid Dout
25
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HM5164400 Series, HM5165400 Series
Fast Page Mode Read-Modify-Write Cycle*
18
t RASP t RP RAS tT t CP t RCD
CAS
t PRWC t CP t CAS t CAS
t RSH t CAS
t CRP
t ASR
t RAD t ASC t RAH t CAH Column 1 t RWD t AWD t CWD t CWL t RCS
t ASC t CAH Column 2 t CPW t AWD t CWD t CWL t RCS
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
Row
WE t RCS t WP t DZC t DS t DH Din t DZO t OED t OEH OE Din 1 t DZO t OED t OEH t WP t DZC t DS t DH Din 2 t DZO t OED t OEH t WP t DZC t DS t DH Din N
t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
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HM5164400 Series, HM5165400 Series
Self Refresh Cycle (L-version)*
t RP
20, 21, 22, 23
t RASS
t RPS
RAS tT t RPC t CP CAS t CRP t CSR t CHS
t WRP WE
t WRH
t OFF Dout High-Z
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HM5164400 Series, HM5165400 Series
Package Dimensions
HM5164400J/LJ Series HM5165400J/LJ Series (CP-32DC)
Unit: mm
32
20.95 21.38 Max
17
10.16 0.13 11.18 0.13
1
3.50 0.26
1.165 Max
0.90 0.26
0.43 0.10 0.41 0.08
1.27
9.40 0.25
0.10
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
28
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2.55 0.46
CP-32DC -- Conforms 1.2 g
0.74
16
HM5164400 Series, HM5165400 Series
HM5164400TT/LTT Series HM5165400TT/LTT Series (TTP-32DC)
Unit: mm 20.95 21.35 Max 32 17
1 0.42 0.08 0.40 0.06 1.15 Max
1.27 0.21
M
16
10.16
0.80 11.76 0.20
0.68
0.10
0.145 0.05 0.125 0.04
0.13 0.05
1.20 Max
0 - 5 0.50 0.10
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-32DC Conforms -- 0.51 g
29
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HM5164400 Series, HM5165400 Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of HitachiOs sales company. Such use includes, but is not limited to, use in life support systems. Buyers of HitachiOs products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
30
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HM5164400 Series, HM5165400 Series
Revision Record
Rev. 0.0 0.1 1.0 Date Jul. 23, 1997 Nov. 1997 Feb. 27, 1998 Contents of Modification Initial issue Change of Subtitle Deletion of Preliminary Drawn by J. Miyake J. Miyake Approved by M. Saeki Y. Takahashi
31
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